1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a wiring layer formed of damascene wiring.
2. Description of the Related Art
FIG. 9 is a plan view of a wiring layer in a semiconductor device including conventional damascene wiring. FIG. 10 is a sectional view taken along the line B-B′ of FIG. 9. A semiconductor device 100 is provided with a wiring layer including a wide wiring 102, and fine wirings 104 and 106 adjacent to each other, in an interlayer insulating film 108 formed on a semiconductor substrate (not shown). Different electric potentials are generally imparted to the fine wirings 104 and 106 adjacent to each other. The wide wiring and the fine wirings are formed by a damascene process. In general, the damascene process requires a surface planarization step of chemical mechanical polishing (CMP) as an essential step. Note that the semiconductor device 100 generally has a multilayer wiring layer, but FIGS. 9 and 10 illustrate a single wiring layer included in the multilayer wiring layer.
In the semiconductor device 100 with the structure as described above, a problem that has not existed in the past arises along with a progress of the miniaturization in recent semiconductor integrated circuits.
In a wiring layout as illustrated in FIG. 9, a distance D and a wiring pitch P between the fine wirings have been made smaller along with the progress of the miniaturization in the recent semiconductor integrated circuits. As a result, there arises a problem that a time-dependent dielectric breakdown (TDDB) lifetime between the fine wirings 104 and 106 adjacent to each other is reduced, or that the fine wirings 104 and 106 adjacent to each other are short-circuited to thereby reduce a yield of the semiconductor device.
JP 2006-165091 A discloses a structure in which a wiring space in a case where a wide wiring and a fine wiring have different electric potentials is secured so as to be larger than a wring space in a case where the wide wiring and the fine wiring have the same electric potential, in a semiconductor device having a wiring layout of the wide wiring and the fine wiring which are adjacent to each other. With this structure, it is assumed that an integration level of a wiring pattern in a semiconductor integrated device can be increased.